FURSOY FURSOY SLICE-1 · RV64IMAFDV Apache-2.0
GitHub · FURSOY/fursoy-cpu

01 / Silicon Microarchitecture & SoC

Fursoy Slice-1

fursoy_s1_core + fursoy_s1_soc — Clean-slate 64-bit out-of-order superscalar RISC-V processor in SystemVerilog (RV64IMAFDV + Zba + Zbb + Zicsr + Zifencei), booting mainline Linux 6.6.50 and BusyBox userspace under Sv39 virtual memory.

VERILATOR BOOT 89.86M cycles (Linux 6.6.50 + BusyBox boot)
CYCLE CONSERVATION 0 CPI leakage (89,861,075 cycle-exact checks)
TIMING CLOSURE 8 / 8 @ 500 MHz Nangate 45nm STA, pre-P&R
STANDARD-CELL AREA 219.43 kGE 111,019 cells across 8 core blocks

02 / Microarchitecture & SoC

Interactive block explorer.

Select any architectural subsystem in the diagram or tabs below to inspect its RTL parameters, queue capacities, and module paths.

2-WIDE FETCH / DECODE / RENAME DISPATCH / WB / RETIRE (2/CYC) L1I + L1D + PTW 64B MMIO & 512B REFILLS 01 · ISA & PRIVILEGE SUBSTRATE RV64IMAFDV + Zba + Zbb + Zicsr + Zifencei M / S / U Modes · medeleg / mideleg · WFI · MRET / SRET 02 · FRONTEND & BRANCH PREDICTION 2-Wide Fetch / Decode / Rename + TAGE-Lite BPU 512-entry BTB (2W) · T0 2K + T1-T4 512 · 108b GHR (3.6875 KiB) · 16-RAS 03 · OOO BACKEND 128 ROB · 8 Checkpoints PRF 160i / 64fp / 48vec IQ 32i / 32m / 16fp / 8v 04 · MEMORY & SV39 DTLB / ITLB + PTW 16 KiB L1I + 16 KiB 8B L1D Non-Destructive L1D Snoop 05 · SOC INTERCONNECT & FIRMWARE (fursoy_s1_soc) 5-Master Priority Crossbar + M-Mode SBI v2.0 256 MiB DRAM (0x8000_0000) · CLINT (10 MHz) · PLIC (31 IRQ) · 16550 UART
ISA & PRIVILEGE

Full General-Purpose & Vector ISA

  • ISA string: RV64IMAFDV + Zba + Zbb + Zicsr + Zifencei (rv64imafdv_zba_zbb_zicsr_zifencei).
  • M/S/U privilege modes with medeleg/mideleg trap delegation, WFI, and MRET/SRET.
FRONTEND & BPU

2-Wide Superscalar & TAGE-Lite

  • 2-wide fetch, 2-wide parallel decode, 2-wide rename, and 2-wide in-order retire.
  • fursoy_s1_bpu.sv: 512-entry BTB (256 sets × 2 ways) + TAGE-Lite (2,048-entry 2-bit bimodal T0 + 4 tagged tables T1–T4 of 512 entries each, 108-bit GHR with circular folded CSRs, 30,208 bits / 3.6875 KiB) + 16-entry checkpointed RAS.
OOO BACKEND

Unified PRFs, Checkpoints & Issue Queues

  • 128-entry ROB (ROB_DEPTH = 128, 4-bit epoch tags) + 8 branch checkpoints (NUM_CHECKPOINTS = 8) for single-cycle speculative RAT, BPU GHR/CSR, and RAS rollback.
  • 160-entry Integer PRF (128 free-list + 32 arch), 64-entry FP PRF (RV64FD), 48-entry Vector PRF (RVV 1.0, VLEN = 256, ELEN = 64, 4 banks × 64-bit).
  • Decoupled Issue Queues: 32-entry Int IQ, 32-entry Mem IQ, 16-entry FP IQ, 8-entry Vector IQ; 64-bit Kogge-Stone ALU & Branch Unit, 3-stage multiplier, hardware divider, FP fma/fdiv/fconv, Vector lanes.
SOC & FIRMWARE

5-Master Crossbar & Custom SBI v2.0

  • fursoy_s1_soc.sv 5-master priority crossbar with anti-starvation threshold & unmapped Access Fault trapping: (1) Uncached MMIO 64-bit, (2) Shared PTW 64-bit, (3) L1I refills 512-bit, (4) L1D demand refills 512-bit, (5) L1D dirty writebacks 512-bit.
  • Address Map: 0x8000_0000–0x8FFF_FFFF (256 MiB DRAM; 0x8000_0000–0x801F_FFFF 2 MiB reserved for M-mode SBI), 0x0200_0000 (CLINT, 10 MHz), 0x0C00_0000 (PLIC, 31 sources), 0x1000_0000 (16550 UART, 115200 baud, PLIC IRQ 1).
  • Custom bare-metal M-mode SBI v2.0 firmware (IMPL_ID = 0xF00501, Version 1; BASE, TIME, SRST, DBCN).

03 / Memory Subsystem & Sv39 MMU

Sv39 translation, 8-bank L1D & PTW coherency.

Hardware-managed virtual translation paired with dual-port data lookups, non-blocking cache misses, and zero-eviction page-table snooping.

TRANSLATION · DATA fursoy_s1_dtlb

Dual-Port Sv39 DTLB

Services Port 2 AGU (loads/stores/AMOs) and Port 3 AGU (loads) in parallel. Pairs a 64-entry 4-way Tree-PLRU base TLB (16 sets, 4 KiB pages) with an 8-entry 2 MiB/1 GiB superpage CAM and a 32-entry Translation Request Table (TRT_DEPTH = 32), enforcing satp/MPRV/SUM/MXR/Svade A/D checks and selective ASID/VA SFENCE.VMA.

TRANSLATION · INSTRUCTION fursoy_s1_itlb

Sv39 ITLB

Provides instruction-fetch address translation via a 64-entry 4-way base TLB (16 sets), an 8-entry 2 MiB/1 GiB superpage CAM, and a 2-entry Instruction Translation Request Table (ITRT) with stale-response suppression.

INSTRUCTION CACHE fursoy_s1_l1i

16 KiB 4-Way L1I Cache

16 KiB, 4-way set-associative (64 sets × 64 B), VIPT-safe instruction cache featuring a conservative next-line prefetcher that automatically aborts at 4 KiB page boundaries, backed by 2 I-MSHRs.

DATA CACHE fursoy_s1_l1d

16 KiB 8-Bank Non-Blocking L1D

16 KiB, 4-way set-associative (64 sets × 64 B), 8-bank (PA[5:3]) non-blocking write-back data cache with a 16-entry Load Queue, 16-entry Store Queue, 4 MSHRs, and a 2-entry Writeback Buffer.

COHERENCY PIPELINE · fursoy_s1_ptw.sv · fursoy_s1_core.sv:722-742

PTW Non-Destructive Dirty-Line Snoop Coherency

Linux page-table updates frequently reside dirty in L1D when a translation miss triggers a walk. Slice-1 resolves PTE hits in 1 cycle without evicting cache lines.

STEP 01 · ARBITRATE

Hardware PTW arbitrates DTLB (priority 1, 4:1 fairness) and ITLB (priority 2) for 3-level Sv39 walks.

STEP 02 · SQ DRAIN

Core waits for backend_sq_empty so committed PTE stores drain cleanly into L1D.

STEP 03 · 1-CYC SNOOP

PTW probes L1D via ptw_snoop_pa_i. On a dirty hit, L1D returns the 64-bit PTE in 1 cycle (ptw_l1d_rsp_data_q) without evicting/invalidating the line and suppresses DRAM traffic; on a miss, PTW reads DRAM via Tier 2 crossbar.

STEP 04 · SFENCE.VMA

SFENCE.VMA drains the store queue and performs a clean-all sweep alongside selective TLB invalidation.

04 / Linux 6.6.50 Boot & Single-Owner CPI

Cycle-exact OS boot & zero CPI leakage.

Workload (results/s1-m9-closeout.json): Mainline Linux 6.6.50 + BusyBox /init running 20 shell functional tests + mem_stress under Verilator (7,180.1 s wall time, 0 kernel panics, 0 oopses, 0 access faults).

TOTAL CYCLES (mcycle) 89,861,075 7,180.1 s Verilator wall time
RETIRED INSTRUCTIONS 76,236,390 2,227,761 U-mode commits · minstret = 76,236,388
SUSTAINED BOOT IPC 0.84838 Across full kernel + BusyBox boot
DEMAND PAGE FAULTS 2,255 1,027 U-mode page faults handled
SYSCALLS / SBI CALLS 1,730 / 1,748 1,730 U-ecalls · 1,748 S-ecalls · 28,538 UART bytes
CPI CONSERVATION CHECKS 89,861,075 / 0 0 conservation errors across boot

Boot Cycle Milestones

283 SBI handoff to Linux
185,993 First satp Sv39 enable (186,042 first virtual PC)
346,605 earlycon UART output
71,815,389 /init launch
74,546,957 BusyBox userspace begin
89,600,540 mem_stress pass
89,811,074 FURSOY_USERSPACE_PASS

8-Bucket Single-Owner CPI Conservation Breakdown

C_productive · 43,079,458 cycles (47.94%)
CPI Bucket Cycles Share Architectural Cause
C_productive 43,079,458 47.94% Active useful graduation / commit cycles
C_br_recover 15,024,530 16.72% Branch misprediction & exception flush recovery
C_idle_other 14,806,625 16.48% WFI idle, non-stalled pipeline drain & bubbles
C_be_rename 5,709,439 6.35% Rename stalls (ROB / Free List / checkpoint capacity)
C_mem_stall 5,549,273 6.18% L1D miss / bank conflict / DTLB-PTW memory stalls
C_be_sched 2,736,785 3.05% Issue queue scheduling / operand stalls
C_serialize 2,450,147 2.73% CSR / SFENCE.VMA / FENCE.I / trap serialization
C_fe_starve 504,818 0.56% Frontend fetch queue empty (L1I / ITLB miss)
Total (mcycle) 89,861,075 100.00% 0 conservation errors · IPC = 0.84838

05 / Physical Synthesis & 500 MHz STA

Nangate 45nm standard-cell timing closure.

Methodology Scope: Synthesized via sv2v v0.0.13 → Yosys 0.33 → OpenSTA 3.1.0 on NangateOpenCellLibrary 45nm Typical (1.10V, 25C), NAND2_X1 = 0.798 um^2, targeting 2.000 ns (500 MHz). Evaluated across standalone 8 core functional logic blocks, SRAMs/PRFs black-boxed, pre-P&R (full-SoC place-and-route and SRAM macro compilation not yet executed).
8 / 8 MET TNS = 0.00 ns 111,019 cells 14,836 DFFs 175,106.74 um^2 (219.43 kGE)
Baseline Arrival Optimized Arrival 2.000 ns (500 MHz)
Module Type Cells DFFs Area (kGE) Baseline Arrival / WNS Optimized Arrival / WNS Timing Closure Optimization
fursoy_s1_branch_unit Comb 3,285 0 4.49 3.712 ns (-1.712 ns) 0.629 ns (+1.371 ns) Cut logic depth 68 → 11–14 levels via parallel Kogge-Stone prefix adders & carry-free target match
fursoy_s1_alu Comb 4,066 0 5.93 3.823 ns (-1.823 ns) 0.994 ns (+1.006 ns) Rebuilt 64-bit adder as Kogge-Stone tree + balanced barrel shifter + tree-structured Zba/Zbb reductions
fursoy_s1_csr Seq 13,438 1,688 25.81 22.776 ns (-21.120 ns) 1.828 ns (+0.133 ns) ABC buffer trees (BUF_X2/X4/X8) & gate sizing closed 510-load high-fanout CSR nets
fursoy_s1_dtlb Seq 50,417 6,515 99.83 11.011 ns (-9.211 ns) 1.249 ns (+0.551 ns) Decoupled registered Tree-PLRU update + ABC fanout buffering
fursoy_s1_itlb Seq 36,238 6,304 77.12 4.057 ns (-2.102 ns) 1.198 ns (+0.602 ns) Decoupled registered Tree-PLRU update + ABC fanout buffering
fursoy_s1_agu Comb 321 0 0.66 2.301 ns (-0.301 ns) 1.901 ns (+0.099 ns) Timing-driven ABC cell sizing closed 64-bit effective-address adder (imm + rs1)
fursoy_s1_ptw Seq 1,765 329 3.67 1.956 ns (+0.005 ns) 0.948 ns (+1.013 ns) Walk state / satp path optimization
fursoy_s1_decode Comb 1,489 0 1.92 0.875 ns (+1.125 ns) 0.663 ns (+1.337 ns) Balanced 2-wide parallel decode paths
Total (8 Core Blocks) All 111,019 14,836 219.43 175,106.74 um^2 8 / 8 MET (TNS = 0.00 ns) Standalone pre-P&R closure @ 500 MHz

06 / Engineering Depth & Roadmap

Silicon bug root-cause & execution discipline.

ROOT-CAUSE ANALYSIS · ~90M-CYCLE OS BOOT CASE STUDY

The mip CSR Read-Modify-Write Livelock

Per RISC-V Privileged Spec §3.1.9, reading mip[9] (SEIP) returns mip_q[9] | irq_seip_i, whereas CSRRS/CSRRC read-modify-write (RMW) operations on mip (0x344) must source only the software-writable mip_q[9] flip-flop.

In the earlier RTL, feeding mip_val directly into the RMW ALU caused a subtle livelock under Linux: while PLIC UART (irq_seip_i) was active, SBI firmware executing csrc mip, (1 << 5) to clear STIP inadvertently read irq_seip_i = 1 and wrote 1 back into the mip_q[9] latch. Even after PLIC cleared the interrupt, SEIP stayed permanently latched at 1, trapping the kernel inside an infinite plic_handle_irq loop.

rtl/core/fursoy_s1_csr.sv:456-458 SystemVerilog 
wire [63:0] rmw_csr_val = (p0_sys_csr_addr_i == 12'h344)
                        ? {mip_val[63:10], mip_q[9], mip_val[8:0]}
                        : old_csr_val;
WORKFLOW

Human vs. AI-Agent Engineering

An AI-agent-assisted workflow was used to accelerate repetitive RTL iterations and Verilator verification scaffolding. Core microarchitectural decisions, 500 MHz timing closure strategies (Kogge-Stone prefix transforms, Tree-PLRU decoupling), and OS-level root-cause debugging were driven by direct manual engineering.

BOUNDARIES & ROADMAP

Pre-Tapeout RTL Stage

Currently at the pre-tapeout RTL stage: full-SoC place-and-route (P&R) and SRAM macro compilation are not yet executed. Upcoming milestones:

  1. Physical FPGA bring-up and on-board Linux console validation.
  2. Architectural trade-off between an inclusive L2 cache and dual-core SMP coherency.